New high-performance carbon nanotube circuits for chips, computers and phones

New high-performance carbon nanotube circuits for devices

New high-performance carbon nanotube circuits for chips, computers and phones

Over the years, there has been a tendency to shrink silicon circuits in order to incorporate more chips in less space. In this way, computers, telephones and other devices have been able to have a higher performance, reaching nowadays their physical limit.

Silicon has been complemented and/or replaced by carbon nanotubes allowing an exponential increase in power. However the truth is that the tubes are quite small and difficult to work with. Different development teams specialised in computers have developed specific methods for collecting nanotubes and aligning them to create a new type of chip.

Carbon nanotubes

Carbon nanotubes are essentially sheets of graphene rolled into a cylinder. Like graphite, they allow electrons to move through them unimpeded, but like silicon they can be semiconductors, turning the flow of electrons on and off in response to a change in voltage.

Individual carbon nanotubes can also be converted into transistors, however it is much easier to create them from groups of aligned tubes. The risk is that some carbon nanotubes become metallic, making the flow of electrons not easily shut off.

To be a good transmitter it will have to be packed densely enough to be able to transmit the current.

Peking University has developed a method for classifying nanotubes so that the metal ratio is no greater than one in a million. And it also aligns them on a silicon wafer at a density of between 100 and 200 per micron, up from 47 achieved by previous researchers. In this way, the method has been shown to be viable for building a much more efficient transmitter.

The density of carbon nanotubes

Researchers say that increasing the density of carbon nanotubes is as easy as adding more solution. And although there is some concern about the waste that may be left by the nanotubes, it is expected that these will be integrated into the market within the next 3-5 years.

This will lead to three-dimensional architectures with many interconnections that allow a huge increase in equipment memory during high-performance processes (such as during the execution of an artificial intelligence algorithm).

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